State of the art non-volatile memory devices are typically constructed by fabricating a field effect transistor in a silicon substrate. The field effect transistor is capable of storing electrical charge either in a separate gate electrode, known as a floating gate, or in a dielectric layer underlying a control gate electrode. Data is stored in a non-volatile memory device by changing the threshold voltage of the field effect transistor through the storage of electrical charge over the channel region of the substrate. For example, in an n-channel enhancement device, an accumulation of electrons in a floating gate electrode, or in a dielectric layer overlying the channel region, creates a high threshold voltage in the field effect transistor. When the control gate is grounded, current will not flow through the transistor, which is defined as a logic 0 state. Conversely, a reduction in the negative charge over the channel region creates a low threshold voltage, possibly negative. In this condition, with the control gate grounded, current will flow through the field effect transistor, which is defined as a logic 1 state.
One particular type of non-volatile memory device is the flash EEPROM (electrically-erasable-programmable-read-only-memory). Flash EEPROMs are a type of device which provide electrical erasing capability. The term "flash" refers to the ability to erase the memory cells simultaneously with electrical pulses. In an erased state, the threshold voltage of the field effect transistor is low and electrical current can flow through the transistor indicating a logic 1 state.
In a flash EEPROM device, electrons are transferred to the floating gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating gate by an overlying control gate electrode. The control gate electrode is capacitively coupled to the floating gate electrode, such that a voltage applied on the control gate electrode is coupled to the floating gate electrode. The flash EEPROM device is programmed by applying a high positive voltage to the control gate electrode and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating gate electrode. The EEPROM device is erased by grounding the control gate electrode, and applying a high positive voltage to either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating gate electrode and into either the source or drain regions in the semiconductor substrate.
In order to obtain increased programming efficiency, EEPROM devices using hot electron injection have been developed that can be programmed by source-side injection. To program an EEPROM device using source-side injection, a select gate electrode is formed overlying a portion of the channel region adjacent to the source region. The select gate electrode is electrically isolated from the control gate electrode, which is formed adjacent to the drain region. During programming, an electric field gradient is established in the channel region such that electrons originating in the source region are accelerated across a potential drop, and are injected onto a floating gate electrode. Programming by source side injection is carried out a low current levels, which permits EEPROM cells to be programmed by charge pumping from a single, low-voltage power supply. Additionally, it has been demonstrated that source-side injection can be many times more efficient than drain side injection. The higher efficiency reduces the amount of time necessary to perform a programming operation.
While programming with sourceside injection, or Fowler-Nordheim tunneling, increases programming efficiency, high-density EEPROM arrays suffer from drain disturbance conditions in cells adjacent to the programmed cell. The access of a certain memory cell is achieved by selecting one bit-line and one word-line, and the cell at the cross point of the selected bit-line and word-line is selected. During programming of the selected cell, a high-positive voltage is applied to both the selected bit-line and selected word-line. However, other memory cells, which are connected to the selected bit-line but on unselected word-lines, are subjected to a high drain voltage with a grounded gate electrode. This is an erase condition which can discharge the floating gate electrodes in unselected cells. The drain disturb condition is aggravated in high-density arrays which place the drain region adjacent to the floating gate electrode. Accordingly, further development of EEPROM arrays is necessary to provide enhanced programming capability, while avoiding drain disturbance conditions.